1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
The DRAM (Dynamic Random Access Memory) is conventionally known widely as one example of a semiconductor memory device. The DRAM includes a memory block where memory cells that are generally storage elements are formed and a peripheral circuit portion where a peripheral circuit which controls the operation of memory cells is formed. If four memory blocks are provided to a conventional DRAM, for example, the peripheral circuit portion has a cross shape. A problem of this conventional DRAM is that signal delay between each memory block and the peripheral circuit portion is not uniform.
According to a layout proposed for solving the problem above, the peripheral circuit portion is concentrated in the central portion surrounded by a plurality of memory blocks. One example of such a layout is shown in FIG. 10.
Referring to FIG. 10, a chip (DRAM) 1 includes eight (8) memory blocks 7a-7h formed on a main surface of a semiconductor substrate 2, and a control circuit portion 3 arranged at a central portion surrounded by the memory blocks. Control circuit portion 3 corresponds to the peripheral circuit portion described above. The length of signal interconnection lines can be made uniform easily by placing memory blocks 7a-7h around control circuit portion 3, and signal delay between control circuit portion 3 and memory blocks 7a-7h can be made uniform.
However, the DRAM shown in FIG. 10 also has a following problem.
The conventional DRAM was not required to achieve a high speed operation which necessitates provision of any heat radiation member. Therefore, it was enough to dissipate heat from a package or a lead frame. As operating frequency of the recent MPU is enhanced, a DRAM operating at a high frequency of 100 MHz or more is required. In this case, generation of heat per unit area at the central portion of chip 1 increases compared with the conventional DRAM, since control circuit portion 3 including any circuit which generates much heat is concentrated in the central portion of chip 1. Consequently, heat is not sufficiently radiated to cause thermal destruction.
If functions of the MPU, Cache, BIST (Built In Self Test) circuit, DRAM for parity and the like can be added after chip 1 is formed, various functions can be added to chip 1 of one type. However, if the structure shown in FIG. 10 is used, those functions as described above cannot be added onto chip 1 selectively since chip 1 is not provided with any pad for interconnection between chips.
Redundancy repair means are respectively provided to memory blocks 7a-7h. However, if any one of memory blocks 7a-7h has a defect which cannot be repaired by the redundancy repair means, the entire chip 1 is determined to be a defective product even if remaining memory blocks are acceptable ones. If the memory block which cannot be repaired can be replaced with an acceptable one, redundancy repairing of chip 1 is possible to improve yield. However, the whole chip 1 is conventionally formed on a single semiconductor chip, and the redundancy repairing of the chip was impossible. As a result, the yield is decreased.